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# Created by write_sdc
# Mon Jul  1 12:14:21 2024
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current_design picorv32
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# Timing Constraints
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create_clock -name clk -period 1.0000 [get_ports {clk}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[0]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[10]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[11]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[12]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[13]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[14]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[15]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[16]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[17]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[18]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[19]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[1]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[20]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[21]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[22]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[23]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[24]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[25]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[26]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[27]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[28]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[29]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[2]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[30]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[31]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[3]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[4]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[5]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[6]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[7]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[8]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {irq[9]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[0]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[10]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[11]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[12]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[13]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[14]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[15]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[16]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[17]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[18]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[19]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[1]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[20]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[21]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[22]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[23]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[24]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[25]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[26]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[27]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[28]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[29]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[2]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[30]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[31]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[3]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[4]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[5]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[6]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[7]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[8]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_rdata[9]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_ready}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[0]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[10]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[11]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[12]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[13]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[14]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[15]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[16]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[17]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[18]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[19]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[1]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[20]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[21]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[22]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[23]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[24]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[25]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[26]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[27]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[28]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[29]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[2]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[30]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[31]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[3]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[4]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[5]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[6]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[7]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[8]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rd[9]}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_ready}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_wait}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_wr}]
set_input_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {resetn}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {eoi[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_addr[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_instr}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_addr[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_read}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wdata[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_write}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wstrb[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wstrb[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wstrb[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_la_wstrb[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_valid}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wdata[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wstrb[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wstrb[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wstrb[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {mem_wstrb[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_insn[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs1[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_rs2[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {pcpi_valid}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[0]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[10]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[11]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[12]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[13]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[14]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[15]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[16]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[17]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[18]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[19]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[1]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[20]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[21]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[22]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[23]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[24]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[25]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[26]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[27]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[28]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[29]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[2]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[30]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[31]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[32]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[33]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[34]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[35]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[3]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[4]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[5]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[6]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[7]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[8]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_data[9]}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trace_valid}]
set_output_delay 0.5000 -clock [get_clocks {clk}] -add_delay [get_ports {trap}]
###############################################################################
# Environment
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# Design Rules
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